1. Field of the Invention
This invention relates to an arithmetic circuit applied to an encoder and a decoder of an error correction code.
2. Background of the Invention
When a digital video signal, a digital audio signal and the like are recorded and reproduced, an adjacent code or Reed-Solomon code is practically normally used as an error correction code. Parity data (redundant data) is generated in an encoder of such error correction signal, and a syndrome is generated in a decoder from a received word including the parity data. Error correction is performed using the syndrome. An arithmetic circuit for processing the elements of a finite field is used as the hardware of the parity generating circuit, the syndrome generating circuit and the error correction circuit. The finite field is a field of pm elements derived from an irreducible polynomial of m-th order, and the case where p=2 is important for the error correction code. Consequently, this invention is applied to the finite field where p=2.
In a conventional arithmetic circuit used in an encoder and a decoder, when multiplication of elements of the finite field is executed, for example, in the case of (.alpha.i, .alpha.j), .alpha.i is stored in a ROM (read-only memory) so as to obtain the exponent i and .alpha.j is similarly stored in a ROM so as to obtain the exponent j. An adder produces the exponent (i+j) which is stored in a ROM, whereby conversion to .alpha.i+j is achieved. In the finite field GF (2m), addition (also subtraction) can be simply implemented using an exclusive-OR gate, but as clearly seen from above-mentioned example, a number of ROMs and registers are required to execute multiplication or division and thereby the scale of the circuit is inevitably enlarged. Moreover, the conventional arithmetic circuit is constituted by dedicated hardware of each kind of polynomial or operation and therefore cannot be used for general purposes.